Balancing between prejudice and fact for Gaming Disorder: Does the existence of alcohol use disorder stigmatize healthy drinkers or impede scientific research?

The inclusion of Gaming Disorder (GD) criteria in the 11th Revision of the International Classification of Diseases (ICD-11) beta draft was recently criticized, and an argument was made for its removal to “avoid a waste of public resources.” However, these misleading statements are believed to be based on under estimation of this ever-growing problem. Such claims may endanger public health and the psychosocial well-being of affected individuals. Thus, the seriousness of the problem was briefly emphasized in our response paper. We provided an overview of how debates of this kind were developed in our region. In addition, we addressed the arguments made on research and children’s rights. The accusation that GD exerts negative impacts on children’s freedom and stigmatizes healthy gamers may arise from a false belief that this new digital media is benign or not addictive. Such statements could be true in some, but not all, cases. Unwillingness to recognize the addictive potential of gaming, as well as insistence on treating GD simply as an individual problem, are reminiscent of the era in which alcoholism was viewed as a personality problem. These dangerous views place affected individuals at greater health risk and further stigmatize them. Formalization of the disorder is also expected to help in standardization of research and treatment in the field. The inclusion of GD in the upcoming ICD-11 is a responsible step in the right direction

A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers

The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply

A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorporated into the design using a tri-level switching scheme and our modified split-capacitor array to achieve the highest switching efficiency while still preserving the symmetry in error tolerance. A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed. The calibration is performed by using the input signal as stimulus and the effectiveness is verified both in simulation and through measured data. The prototype achieves a 67.4dB SNDR at 50MS/s, while dissipating 2.1mW from a 1.2V supply, leading to FoM of 21.9fJ/conv.-step at Nyquist frequency.MIT Masdar Progra

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.Comment: Accepted to the 57th Design Automation Conference (DAC 2020); 6 pages, 8 figure

FOOT ARCH STRAIN OF EXCESSIVE PRONATORS DURING TWO-LEGS AND ONELEG STANDING AND WALKING

INTRODUCTION: The movement of plantar fascia under the foot has been characterized by foot arch strain in vitro (Kogler, Solomonidis, & Paul, 1995). The characteristics of the foot arch strain under the static and dynamic conditions in excessive pronators are not well known. Therefore, the purpose of this study is to investigate the foot arch strain during two legs, one-leg standing and walking in excessive pronation

Materials and extracellular matrix rigidity highlighted in tissue damages and diseases: Implication for biomaterials design and therapeutic targets

Rigidity (or stiffness) of materials and extracellular matrix has proven to be one of the most significant extracellular physicochemical cues that can control diverse cell behaviors, such as contractility, motility, and spreading, and the resultant pathophysiological phenomena. Many 2D materials engineered with tunable rigidity have enabled researchers to elucidate the roles of matrix biophysical cues in diverse cellular events, including migration, lineage specification, and mechanical memory. Moreover, the recent findings accumulated under 3D environments with viscoelastic and remodeling properties pointed to the importance of dynamically changing rigidity in cell fate control, tissue repair, and disease progression. Thus, here we aim to highlight the works related with material/matrix-rigidity-mediated cell and tissue behaviors, with a brief outlook into the studies on the effects of material/matrix rigidity on cell behaviors in 2D systems, further discussion of the events and considerations in tissue-mimicking 3D conditions, and then examination of the in vivo findings that concern material/matrix rigidity. The current discussion will help understand the material/matrix-rigidity-mediated biological phenomena and further leverage the concepts to find therapeutic targets and to design implantable materials for the treatment of damaged and diseased tissues

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver

This paper demonstrates a four-channel transceiver chip for medical ultrasonic imaging, interfacing to the capacitive micromachined ultrasonic transducers (CMUTs). The high-voltage transmitter (Tx) uses a three-level pulse-shaping technique with charge recycling to improve the power efficiency. The design requires minimum off-chip components and is scalable for more channels. The receiver is implemented with a transimpedance amplifier (TIA) topology and is optimized for tradeoffs between noise, bandwidth, and power dissipation. The test chip is characterized with both acoustic and electrical measurements. Comparing the three-level pulser against traditional two-level pulsers, the measured Tx efficiency shows 56%, 50%, and 43% more acoustic power delivery with the same total power dissipation at 2.5, 3.3, and 5.0 MHz, respectively. The CMUT receiver achieves the lowest noise efficiency factor compared with that of the literature (2.1 compared to a previously reported lowest of 3.6, in units of mPA ·√(mW/Hz). In addition, the transceiver chip is tested as a complete system for medical ultrasound imaging applications, in experiments including Tx beamformation, pulse-echo channel response characterization, and ultrasonic Doppler flow rate detection.Semiconductor Research Corporation. Focus Center for Circuit and System Solutions (C2S2